Neuromorphic Computing in 2026: Real at Microwatts, Not for LLMs

I spend my days making general-purpose compute boot faster and cost less. So when someone tells me a chip does inference at a thousandth of the energy of a GPU, my first question is not "how" but "on what, measured against which GPU, at what batch size". Neuromorphic computing has been answering that question badly for fifteen years, mostly because the people asking it were not the people building it.

This year the answers got more honest, and the picture that emerges is more interesting than either the hype or the dismissal. Neuromorphic hardware is shipping in production for one class of workload, has gone quiet at the company most associated with it, and has been definitively ruled out for the workload everyone actually cares about. I want to lay out all three with numbers, because "brain-inspired" is a phrase that has done a lot of unearned work.

First, what the word means

Two very different things get called neuromorphic, and conflating them is the source of most confusion.

The strict meaning is spiking neural networks on event-driven hardware. Neurons hold state, integrate inputs over time, and emit a spike only when a threshold is crossed. Nothing happens, and no energy is spent, unless something spikes. Intel's Loihi, SpiNNaker, BrainChip's Akida, SynSense and Innatera are in this family. The efficiency argument is entirely about sparsity: if only 5% of neurons are active at any moment, you do 5% of the work.

The loose meaning is any chip that co-locates memory and compute to avoid the DRAM round-trips that dominate energy in a GPU. IBM's NorthPole is the flagship. IBM calls it "brain-inspired" and it is a superb chip, but it runs ordinary quantised convolutional and transformer networks, not spikes. The Nature roadmap published by twenty-three of the field's leaders in January 2025 treats tightly coupled memory and compute as one of five defining features, so IBM is within their definition. Just know that when NorthPole beats a GPU, it is not because of spikes.

The hardware in 2026

System	What it is	Scale	Status
Intel Loihi 2	Digital SNN chip, Intel 4 process, up to 1M neurons and 120M synapses per chip	Hala Point: 1,152 chips, 1.15B neurons, 2.6 kW, at Sandia	Research access only; software archived May 2026
SpiNNaker2	152 Arm Cortex-M4F cores per chip, 22nm, event-driven	Sandia's Braunfels: 1,152 chips, 175M neurons; Leipzig: 656,640 cores	Commercial via SpiNNcloud; EU-funded
IBM NorthPole	12nm inference chip, 256 cores, all memory on-die, no DRAM	288-card rack: 30 kW, 115 peta-ops INT4	Research; $48M Air Force contract to 2027
BrainChip AKD1500	SNN co-processor, 22nm, under 300 mW	Single chip	Production shipments since June 2026
Innatera Pulsar	Mixed-signal SNN microcontroller, 28nm	Single chip, reportedly under $5 in volume	Launched May 2025; partner devices at CES 2026
SynSense Xylo / Speck	Sub-mW audio and vision SNN chips, Speck integrates an event camera	Single chip	Shipping

Three things in this table deserve comment.

Intel went quiet. On 13 May 2026 Intel archived every Lava repository, the open-source framework that was the only public way to program Loihi. The notice promises "a new SDK and next generation Loihi processor" built on "open-standard AI frameworks", which I read as an admission that a bespoke programming model was a strategic mistake. You will see "Loihi 3" specifications circulating with a process node and a launch quarter. I could not find any of them on an Intel property, and Intel's own neuromorphic page still lists Loihi 2 as current. Treat those as fabricated until Intel says otherwise. Meanwhile Hala Point at Sandia is doing real work: their 2025 report describes running the entire fruit-fly connectome, about 140,000 neurons and 50 million synapses, on 12 Loihi 2 chips at more than 100 times the speed of conventional simulation.

Europe is building the big machines. SpiNNcloud's Dresden system has over five million Arm cores. Sandia bought one. Leipzig bought one for drug discovery. The design choice is telling: SpiNNaker2 uses ordinary Arm microcontroller cores with accelerators, so it runs conventional code too. That is a hedge against the programming-model problem that killed Lava, and it is why I would bet on SpiNNaker outliving Loihi as a research platform.

The commercial products are tiny. AKD1500, Pulsar and Xylo are all sub-watt, and in Pulsar's and Xylo's cases sub-milliwatt. They do keyword spotting, radar presence detection, audio scene classification and vibration monitoring. Innatera quotes 600 µW for radar presence detection. Frontgrade Gaisler is putting Akida in a radiation-hardened space processor. This is the "always-on sensor" niche, where the device is asleep 99% of the time and the whole point is to spend nothing while waiting. It is the one place where the sparsity premise is naturally true, and it is where the technology is actually shipping.

The benchmark numbers, honestly

The field finally has a shared benchmark. NeuroBench, published in Nature Communications in February 2025, has an algorithm track that measures accuracy and effective operations, and a system track that measures real hardware. The algorithm-track baselines are the most useful numbers in this whole post, because they show the accuracy gap that vendors never mention.

Keyword few-shot class-incremental (session-average accuracy) 89.3% 75.3%

Event-camera object detection (mAP, scaled to 100) 0.429 0.271

Primate motor prediction (R², scaled to 100) 0.593 0.593

Source: NeuroBench algorithm-track baselines, Yik et al., Nature Communications 16:1545 (2025).

The pattern is consistent across the literature: spiking networks are competitive on low-dimensional, temporally structured signals, and behind on anything resembling vision at scale. The system-track results are where the efficiency shows up. SynSense's Xylo matched a CPU baseline on audio scene classification (79.9% versus 79.6%) at about 61 times less dynamic inference power than an Arduino-class microcontroller. A Loihi 2 QUBO solver drew 37 times less power than the best CPU solver. Both are real. Both are also small, sparse problems.

The best Loihi paper of the year makes the same point from the other direction. An October 2025 keyword-spotting study found Loihi 2 up to 18 times faster and 250 times more energy-efficient than a Jetson Orin Nano on the Spiking Heidelberg Digits tasks with near-zero accuracy loss. That is the sparse, temporal, small-model regime. A March 2025 paper that ran a 370-million-parameter matmul-free language model on Loihi 2 found roughly three times the throughput and half the energy of an edge GPU. Three times, not three hundred. That is what happens when activity stops being sparse.

Two structural critiques from the research community are worth knowing because they explain the numbers. First, the training problem: spikes are not differentiable, so SNNs are trained with surrogate gradients and backpropagation through time, whose memory scales with the number of timesteps. Eshraghian and colleagues wrote the definitive treatment. It works, but it is slower and fussier than training an ordinary network, and the accuracy gap above is partly a training-maturity gap. Second, a January 2026 runtime model fitted to Loihi 2 measurements found the chip is communication-bound, limited by network-on-chip congestion rather than compute. Intel's own 2021 technical brief had flagged inter-chip congestion as the limit on the previous generation. The energy advantage is real per operation and gets eaten by routing as the model grows.

What it looks like in code

If you want to build intuition, the software side is mature enough to run on a laptop in an afternoon. snnTorch is the most approachable, sits on top of PyTorch, and exports to the Neuromorphic Intermediate Representation, a 2024 Nature Communications standard that eleven simulators and four hardware targets accept. This is a spiking convolutional network from the snnTorch README, with the surrogate gradient that makes training possible:

import torch, torch.nn as nn
import snntorch as snn
from snntorch import surrogate, utils

num_steps, beta = 25, 0.5                      # timesteps; membrane decay
spike_grad = surrogate.fast_sigmoid()           # differentiable stand-in for the spike

net = nn.Sequential(
    nn.Conv2d(1, 8, 5), nn.MaxPool2d(2),
    snn.Leaky(beta=beta, init_hidden=True, spike_grad=spike_grad),
    nn.Conv2d(8, 16, 5), nn.MaxPool2d(2),
    snn.Leaky(beta=beta, init_hidden=True, spike_grad=spike_grad),
    nn.Flatten(), nn.Linear(16 * 4 * 4, 10),
    snn.Leaky(beta=beta, init_hidden=True, spike_grad=spike_grad, output=True),
)

data_in = torch.rand(num_steps, 1, 1, 28, 28)   # [time, batch, channel, H, W]
utils.reset(net)                                 # clear membrane state
spikes = [net(data_in[t])[0] for t in range(num_steps)]

The thing to notice is the outer loop over num_steps. Every input is presented as a sequence, the network carries membrane state between steps, and the output is a spike train you decode by counting. That loop is where the memory cost of training lives, and it is also where the efficiency comes from on hardware that only does work when a spike arrives. The whole field is in that one loop.

Be aware that the NIR authors themselves report that recurrent models "produced somewhat diverging activation patterns and accuracies" across platforms. Portability is real for feed-forward networks and approximate for anything with state, which is a problem when state is the point.

NorthPole, and why it is the honest answer to "can it run LLMs"

IBM's NorthPole is the chip I find most interesting, precisely because it does not pretend to be a brain.

The 2023 Science paper reported ResNet-50 inference 25 times more energy-efficient than a GPU on the same 12nm process, with 22 times lower latency, by putting all memory on-die and never touching DRAM. In September 2024 they ran a 3-billion-parameter language model at 4-bit precision under one millisecond per token, with 16 chips in a 2U server producing 28,356 tokens per second, and claimed roughly 73 times better tokens-per-second-per-watt than a 4nm GPU in the low-latency regime. In November 2025 they scaled to 288 cards across 18 servers, 30 kilowatts, running one 70-billion-parameter instance per rack.

Read that last number again. One 70B model per 42U rack at 30 kW. A single H100 node runs that model in 8U at around 10 kW with batching. NorthPole wins decisively on latency per token at batch size one, and it wins on energy per token in that regime. It does not win on throughput per rack, and it cannot hold a frontier-scale model at all, because everything has to fit in on-chip SRAM. Dharmendra Modha, who leads the project, said it directly in 2023: "We can't run GPT-4 on this." That has not changed.

So the answer to "will neuromorphic replace GPUs for LLM inference" is no, from the people who have come closest. The answer to "is there a low-latency, low-batch inference niche where memory-on-die wins" is yes, and the Air Force is paying $48 million to find out how big it is.

What I would tell someone deciding today

The market forecasts are useless for decisions. Yole's 2024 report says $412 million for neuromorphic compute by 2029; other analysts say figures five times higher for 2026. When estimates disagree by 5x, the honest conclusion is that nobody knows, and the number is small either way.

What I think is defensible:

• If your workload is an always-on sensor with a power budget in milliwatts, neuromorphic silicon is shipping, it is cheap, and it is the right answer. Keyword spotting, presence detection, vibration anomaly detection, event-camera triggers. Buy Pulsar or Akida or Xylo and benchmark them against your best microcontroller-plus-tiny-model baseline. You will probably see a 10x or better energy win with a modest accuracy cost.
• If your workload is vision or language at datacenter scale, nothing in this post applies to you and nothing will for years. The efficiency claims are for sparse regimes you are not in, the accuracy gap is real, and the programming model is immature. Compute-in-memory chips like NorthPole and d-Matrix are a more plausible path than spikes, and they are still research or early product.
• If you are choosing a research platform, SpiNNaker2 is the safer bet than Loihi right now, because Intel's software is archived and its next chip is unannounced.

The Nature roadmap authors framed the field as waiting for its "AlexNet moment", the result that makes everyone switch. I do not think that moment is coming for the datacenter. I think it already quietly happened at the sensor edge, on chips that cost less than a coffee, and almost nobody noticed because a 600-microwatt radar detector does not make headlines.

---

Related: Post-Quantum Migration in 2026, another field where the honest numbers are more interesting than the headlines.